FIG. 1 illustrates a comparator that comprises several capacitors. Two pairs of voltages are provided. The first pair is VIP 115 and VIN 19 which represent the positive and negative inputs. The second pair is VRP 116 and VRN 18 which represent the positive and the negative reference inputs. Two capacitors 120 and 16 are used to receive input signals. An NMOS transistor 118, controlled by the phase I signal 117, is electrically connected to the VRP 116 and terminal 119 of the capacitor 120. An NMOS transistor 111, controlled by the phase I signal 17, is electrically connected to the VRN 18 and terminal 110 of the capacitor 16. A phase II signal 113 that controls an NMOS transistor 114 and an NMOS transistor 112 is also provided. The NMOS transistor 114 is electrically connected to the VIP 115 and terminal 119. The NMOS transistor 112 is electrically connected to the VIN 19 and terminal 110. NMOS transistor 122, controlled by phase I signal 123, provides common mode voltage 121 to output terminal 124 of capacitor 120. Moreover, NMOS 125 transistor, controlled by phase I signal 13 provides common mode voltages 14 to output terminal 15 of capacitor 16. The output terminals 124 and 15 are electrically connected to a latch 11 which provides an output 12. The output 12 shows the comparison result between input signals. Typically, a latch with positive feedback is used to lock the difference between the voltage on terminals 124 and 15. There are provided two steps to control the phase I signals 123, 13, 117, and 17, and phase II signal 113. In phase I, the terminals 124 and 15 receive the common voltage reference. Terminals 119 and 110 receive the input reference voltages VRP 116 and VRN 18, respectively. In phase II, the switches 114 and 112 are enabled, i.e. the transistors are turned on. The input voltages VIP 115 and VIN 19 are sent to the terminals 119 and 110, respectively. Thus, if the voltage difference between VIP 115 and VIN 19 is greater than the voltage difference between VRP 116 and VRN 18, then the output 12 may be in high state. For example, if VIP 115, VIN 19, VRP 116, VRN 18 are 3V, 2V, 5V and 4.5V respectively, then terminal 15 has a voltage of −2.5V and terminal 124 has a voltage of −2V. The voltage of terminal 124 is 0.5V higher than that of terminal 15, which is to the same as the result of the equation [(VIP−VIN)−(VRP−VRN)].
The example in FIG. 1 uses many capacitors. This means the embodiment involves more complex processing steps, i.e. expensive mixed-mode process.
FIG. 2 shows a comparator introduced in the paper by T. B. Cho and P. R. Gray, entitled “A 10b, 20 Msample/s, 35 mW Pipeline A/D Converter,” IEEE JSSC, Vol. 30, No. 3, March 1995. The disclosure of which is herein incorporated by reference. The comparator is composed of MOS transistors. This comparator utilizes a dynamic cross-coupled inverter latch to eliminate the static power dissipation. The dynamic comparator uses a positive feedback latch. The positive feedback latch comprises (1) PMOS transistors 218 and 221 which are electrically connected to the NMOS transistors 215 and 25 via the wires GP 219 and GN 220; (2) a pair of NMOS transistors 212 and 29 which are electrically connected to receive the input reference voltages VRN 211 and VRP 210; and (3) a pair of NMOS transistors 27 and 213 which are connected to receive the input reference voltages VIN 26 and VIP 214. Furthermore, a PEV signal 23 is electrically connected to both the gates of PMOS transistors 22 and 217, and also NMOS transistors 24 and 216, to reset the latch before the comparator begins to evaluate.
A transistor string which comprises the PMOS transistor 22, NMOS transistor 24, NMOS transistor 25 and NMOS transistor 27 is orderly arranged in serial. The power connection 21 is connected to the PMOS transistor 22. The ground 28 is connected to the source of the NMOS transistor 27. Another string which comprises the PMOS transistor 221, NMOS transistor 24, NMOS transistor 25 and NMOS transistor 210 is orderly arranged in serial. The power connection 21 is electrically connected to the PMOS transistor 221. The ground 28 is electrically connected to the source of the NMOS transistor 210.
A transistor string which comprises the PMOS transistor 217, NMOS transistor 216, NMOS transistor 215 and NMOS transistor 213 is sequentially arranged. The power connection 21 is connected to the PMOS transistor 217. The ground 28 is connected to the source of the NMOS transistor 213. Another string which comprises the PMOS transistor 218, NMOS transistor 216, NMOS transistor 215 and NMOS transistor 212 is sequentially arranged. The power connection 21 is connected to the PMOS transistor 218. The ground 28 is connected to the source of the NMOS transistor 212. When the PEV signal 23 is in low state, the PMOS transistors 22 and 217 are turned on. The power connection 21 provides current to the GP 219 and GN 220. The NMOS transistors 216 and 24 are turned off during the low state. No current is leaked to the ground 28 in the path of NMOS transistors 25, 27 and 29 or the path of NMOS transistors 215, 212 and 213. As mentioned in the reference by Cho et al., the NMOS transistors 213, 212, 29, 27 are all biased in triode region. The conductance G1 and G2 thereof are given by
      G    ⁢                  ⁢    1    =      kp    ⁡          [                                                  W              ⁢                                                          ⁢              1                        L                    ⁢                      (                          VIP              -              Vth                        )                          +                                            W              ⁢                                                          ⁢              2                        L                    ⁢                      (                          VRN              -              Vth                        )                              ]      wherein Vth is the threshold voltage of the NMOS transistor, kp is a constant related to the physical characteristics of the transistor and W1, W2 and L are the dimensions of the transistor.
      G    ⁢                  ⁢    2    =      kp    ⁡          [                                                  W              ⁢                                                          ⁢              1                        L                    ⁢                      (                          VIN              -              Vth                        )                          +                                            W              ⁢                                                          ⁢              2                        L                    ⁢                      (                          VRP              -              Vth                        )                              ]      wherein Vth is the threshold voltage of the NMOS transistor, kp is a constant related to the physical characteristics of the transistor and W1, W2 and L are the dimensions of the transistor.
The comparator changes its state when the differential inputs exceed the comparator threshold voltage. The comparator threshold voltage is provided by
      Vin    ⁡          (      threshold      )        =                    W        ⁢                                  ⁢        2                    W        ⁢                                  ⁢        1              ·                  ⁢    Vref  wherein Vin=VIP−VIN and Vref=VRP−VRN.
The comparator in FIG. 2 saves power by using a dynamic approach. It is well known to those skilled in the art that the process variations and mismatches can result in greater offset voltage in typical dynamic cross-coupled inverter latches.
In U.S. Pat. No. 5,668,486 to Brehmer, entitled “Strobed comparator for a large common mode range,” a comparator having a large common mode range is described. The disclosure of which is herein incorporated by reference. It utilizes a high-swing folded-cascade architecture to achieve an improved dynamic range. By using a folded cascade design, a wide dynamic range of operations can be obtained. However, this design requires the normal and enhancement transistors which can complicate the manufacturing process and increase the cost. Moreover, this design also suffers the offset and mismatch problems.
In U.S. Pat. No. 6,144,231 to Goldblatt, entitled “High Speed Dynamic Latch Comparator,” a comparator circuit design is disclosed. The entire disclosure of which is herein incorporated by reference. An additional differential amplifier circuitry with pull-down devices is electrically connected to the GN 220 and GP 219 in FIG. 2. The pull-down devices accelerate the positive feedback mechanism and increase the comparing operation. As mentioned in this disclosure, the voltage error is primarily caused by current differences. The current differences relate to the gate threshold voltage (Vt) and the susceptance (B). The voltage error can be derived from the following equation:
  err  =      V    ⁢                  ⁢          2      ⁡              [                  1          -                                    B              ⁢                                                          ⁢                              1                ·                                                                  ⁢                                                      (                                          Vgs                      -                                              Vt                        ⁢                                                                                                  ⁢                        1                                                              )                                    2                                                                    B              ⁢                                                          ⁢                              2                ·                                                                  ⁢                                                      (                                          Vgs                      -                                              Vt                        ⁢                                                                                                  ⁢                        2                                                              )                                    2                                                                    ]            wherein V2 is the input voltage; B1 and B2 are the susceptance of the primary pull-down devices; and Vt1 and Vt2 are the threshold voltages.
Enlarging the dimensional size of the pull-down devices can minimize the voltage error. However, this design requires extra elements to overcome the variation in the primary pull-down devices.